This invention relates to circuit design, and more particularly, to circuit design tools that support devices in which phase-locked loop circuits can be dynamically reconfigured.
Complex integrated circuit designs are typically created using circuit design tools such as computer-aided-design (CAD) tools. For example, logic designers that are designing custom logic circuits for programmable logic devices (PLDs) use PLD design tools to help create their designs. Designers of application specification integrated circuits (ASICs) and other integrated circuits also use CAD tools during the design process.
After a circuit designer has input a desired circuit design, the circuit designer uses the CAD tools to generate an output in a desired format. The CAD tools may, for example, use the specified design to generate configuration data for a programmable logic device. The configuration data can be loaded into the programmable logic device to create a custom logic circuit implementation of the circuit design.
A logic designer may use CAD tools to design integrated circuits with real-time dynamic reconfiguration capabilities. For example, a logic designer may be able to use CAD tools to generate one or more phase-locked loop initialization files, each of which corresponds to a particular phase-locked loop configuration, for integrated circuits that support real-time dynamic reconfiguration of phase-locked loop circuitry.
Conventional CAD tools require that logic designers perform design compilations for each phase-locked loop configuration (e.g., to generate corresponding phase-locked loop initialization files) and a final design compilation using the initialization files together with the actual design of the integrated circuit. Each compilation typically requires synthesis operations and a fitting process (e.g., a place and route process) to generate an appropriate output and can therefore take a relatively long time to execute. Because the number of required design compilations increases with the number of phase-locked loop configurations when using conventional CAD tools, the conventional CAD tools can require an undesirably long period of time to complete design compilation.
It would therefore be desirable to be able to provide improved circuit design tools that support devices with phase-locked loop reconfiguration capabilities.